DDS, FPGA, VHDL, MATLAB/Simulink, Low Power Consump- tion


In this paper, we will describe the synthesis of the Direct Digital Syn- thesis (DDS) circuit using the VHDL language. Nowadays the DDS is being

used widely in the fields of telecommunications, including signal generator cir- cuits. The DDS circuits are used to generate analog signals with the use of digi- tal circuits. This work aims to present the implementation of DDS with the

VHDL language, which offers compatibility with FPGA devices. Initially, the VHDL code was generated automatically via Matlab/Simulink model, designed by using HDL Coder components, which are compatible with VHDL. The VHDL code is modified in order to optimize the automatically generated code and the performance of the DDS circuit, Due to this optimization done on VHDL code about 15% improvement in power consumption and reduction of resource utilization is achieved.



First Page


Last Page


Included in

Business Commons



To view the content in your browser, please download Adobe Reader or, alternately,
you may Download the file to your hard drive.

NOTE: The latest versions of Adobe Reader do not support viewing PDF files within Firefox on Mac OS and if you are using a modern (Intel) Mac, there is no official plugin for viewing PDF files within the browser window.