Session
Mechatronics, Sciences in Energy Efficiency Engineering, System Engineering and Robotics
Description
Usage of programmable logic devices PLD has increased in the latest years because of the ability to quickly implement complex types of electronic systems while reducing cost and time of synthesis. This technology enables dynamic reconfiguration of different applications according to specific requirements. Also, power consumption and its loss is becoming an increasingly important requirement in the design of systems for portable applications fed by batteries.
Other factors to be taken into account in the consumption of power are elements that are used for manufacturing, packaging, and cooling systems. Power consumption must be taken into consideration especially for wireless applications where battery technologies provide power 20 W/h and voltage 1.2 volts. Despite improvements in battery technology, the development of methods for reducing power consumption plays a decisive role in portable applications.
Therefore, modeling of power consumption has become a requirement with the highest impact in the performance of FPGA elements. Despite generated models of the different manufacturers of these elements, this article will appear comparisons of models based on experimental measurements performed on both CPLD and FPGA elements. Based on these models is selected to simulate a system that will be implemented in two elements and see how reduced power consumption, without affecting system performance. Experimental results show that FPGA elements have better performance and significantly reduce the power consumption.
Keywords:
models, power consumption, CPLD/FPGA
Proceedings Editor
Edmond Hajrizi
ISBN
978-9951-437-51-6
First Page
12
Last Page
19
Location
Durres, Albania
Start Date
28-10-2016 9:00 AM
End Date
30-10-2016 5:00 PM
DOI
10.33107/ubt-ic.2016.40
Recommended Citation
Ibro, Marsida and Karçanaj, Luan, "Models for reducing power consumption in CPLD and FPGA devices" (2016). UBT International Conference. 40.
https://knowledgecenter.ubt-uni.net/conference/2016/all-events/40
Models for reducing power consumption in CPLD and FPGA devices
Durres, Albania
Usage of programmable logic devices PLD has increased in the latest years because of the ability to quickly implement complex types of electronic systems while reducing cost and time of synthesis. This technology enables dynamic reconfiguration of different applications according to specific requirements. Also, power consumption and its loss is becoming an increasingly important requirement in the design of systems for portable applications fed by batteries.
Other factors to be taken into account in the consumption of power are elements that are used for manufacturing, packaging, and cooling systems. Power consumption must be taken into consideration especially for wireless applications where battery technologies provide power 20 W/h and voltage 1.2 volts. Despite improvements in battery technology, the development of methods for reducing power consumption plays a decisive role in portable applications.
Therefore, modeling of power consumption has become a requirement with the highest impact in the performance of FPGA elements. Despite generated models of the different manufacturers of these elements, this article will appear comparisons of models based on experimental measurements performed on both CPLD and FPGA elements. Based on these models is selected to simulate a system that will be implemented in two elements and see how reduced power consumption, without affecting system performance. Experimental results show that FPGA elements have better performance and significantly reduce the power consumption.