Article Title

Direct Digital Synthesis Optimization Based on VHDL Code

Authors

Marsida Ibro, Aleksander Moisiu UniversityFollow

Keywords

DDS, FPGA, VHDL, MATLAB/Simulink, Low Power Consump- tion

Abstract

In this paper, we will describe the synthesis of the Direct Digital Syn- thesis (DDS) circuit using the VHDL language. Nowadays the DDS is being

used widely in the fields of telecommunications, including signal generator cir- cuits. The DDS circuits are used to generate analog signals with the use of digi- tal circuits. This work aims to present the implementation of DDS with the

VHDL language, which offers compatibility with FPGA devices. Initially, the VHDL code was generated automatically via Matlab/Simulink model, designed by using HDL Coder components, which are compatible with VHDL. The VHDL code is modified in order to optimize the automatically generated code and the performance of the DDS circuit, Due to this optimization done on VHDL code about 15% improvement in power consumption and reduction of resource utilization is achieved.

DOI

10.33107/ijbte.2021.6.3.22

First Page

1

Last Page

8

Recommended Citation

Ibro, Marsida (2021) "Direct Digital Synthesis Optimization Based on VHDL Code," International Journal of Business and Technology: Vol. 9: Iss. 1, Article 24.
DOI: 10.33107/ijbte.2021.6.3.22
Available at: https://knowledgecenter.ubt-uni.net/ijbte/vol9/iss1/24